FPGA Design -- Clock Generator

Project

Clock Generator/LED Flasher

No:
1

Date:
09-Mar-2001

Design a circuit that can convert a 24Mhz clock input into a 10 Hz clock output. The circuit specification is as follows:

Pin Direction Description

CLK_IN
IN
This pin should be connected to the 24Mhz on board oscillator at location P77.

CLK_OUT
OUT
This pin should have a 10Hz output signal on it and be connected to the on-board LED at location P49. It must have a 50% duty cycle.

RESET*
IN
This active low pin should stop the output on the CLK_OUT pin and reset CLK_OUT to a logic true condition. Connect it to the test jumper at location P61.

Ok, so this isn't a very glamorous project but it serves to familiarize yourself with the tools and the equipment. Its also darn difficult to screw up :-).

Purpose

The purpose of this project is two fold, first it goes through the process of creating a file that you can download into and FPGA (tool checkout) and it also validates that the board you are using is working. I've got both the XESS board and the BurchEd FPGA demonstrator boards. (currently I've only spec'd the constraints for the BurchEd board)

Discussion

The clock generator is a very straight-forward 3 pin circuit. The primary feature of this design will be a counter that divides the 24Mhz input clock by 2,400,000 to produce the output. Think about the requirement for a 50% duty cycle in your design.

Going Further

As I said in the beginning, this is more about learning how to use the tools than to design with VHDL but there are some things you can do that make this circuit a bit more interesting.

Create a two-phase clock where two pins are being driven in opposite directions.

Make the clock output speed settable based on an input pin (1Hz, 10Hz, 100Hz, etc)

For a really good time make the circuit read 4 BCD coded switches and output a square wave at the frequency of set by those switches.

Copyright © 2001, Chuck McManis, All Rights Reserved

Project		Clock Generator/LED Flasher
No:	1
Date:	09-Mar-2001

Pin	Direction	Description
CLK_IN	IN	This pin should be connected to the 24Mhz on board oscillator at location P77.
CLK_OUT	OUT	This pin should have a 10Hz output signal on it and be connected to the on-board LED at location P49. It must have a 50% duty cycle.
RESET*	IN	This active low pin should stop the output on the CLK_OUT pin and reset CLK_OUT to a logic true condition. Connect it to the test jumper at location P61.