VHDL Source code for GEN_S0

-- Generate Segment 0, in one Gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity GEN_S0 is
    Port (data : in std_logic_vector(3 downto 0);
	  seg : out std_logic);
end GEN_S0;

architecture behavioral of GEN_S0 is 
begin
    with data select
	 seg <= '0' when "0001",
		'0' when "0100",
		'0' when "1101",
		'0' when "1011",
		'1' when others;
end behavioral;