VHDL Source code for GEN_S6

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity GEN_S6 is
    Port ( data : in std_logic_vector(3 downto 0);
           seg : out std_logic);
end GEN_S6;

architecture behavioral of GEN_S6 is

begin
    with data select
	seg <= '0' when "0001",
		 '0' when "0000",
		 '0' when "0111",
		 '0' when "1100",
		 '1' when others;
end behavioral;