FPGA Design -- HEX Display

Project

Two digit HEX counter with LED Display

No:
4

Date:
10-Mar-2001

Design an 8 bit counter that displays its current count on two LED displays. The counter should count at a rate of 10 counts/second. Use the CLOCK_10HZ and HEX_DISPLAY entities in this project. The pin-out for this chip is as follows:

Pin Direction Description

SRC_CLK
IN
This is a 24Mhz input clock.

DISPLAY0[6..0]
DISPLAY1[6..0]
OUT
Two seven segment displays. Display zero is the high order display and display one is the low order display.

CLR
IN
When asserted "low" this pin should reset the count to "00."

RUN IN When this pin is asserted "high" the counter runs, when it is "low" the counter should hold its count.

DIR IN When this pin is asserted "high" the counter should count "up" (from 0 up), when it is "low" the counter should count down from "FF" to 0.

This project creates another bit of eye-candy for you to look at, a couple of digits counting up, or down, in hexadecimal.

Purpose

The neat thing about this project is that it gets a bit more complicated in what it combines. It leads naturally into the next project (a multi-digit display) and has a twist that you need are including both a reset circuit (CLR) and a gating circuit (RUN).

Discussion

The hex counter provides an 8 bit count for the incoming clock. With a minor modification it can be adapted to be a pulse accumulator, counting the number of pulses that happen in unit time.

In this circuit the SRC_CLK pin is again the 24Mhz master clock from the SPARTAN2+ board. If you're using the XESS board then it would be the 12Mhz clock on that board, The RUN pin should enable/disable the counting logic and the DIR pin controls whether the counter goes up or down.

Going Further

The basic up/down counter is a staple in a lot of circuits you may build. In robots they are used by encoders to determine wheel position. Some other ideas::

Conver the counter to a frequency counter by gating the RUN/CLR pins with another pin.

Have the counter recognize that it is at the upper or lower limit of its count and have it automatically reverse direction.

Have the counter do leading zero suppression so the counts between 0 - f have only one digit illuminated.

Copyright © 2001, Chuck McManis, All Rights Reserved

Project		Two digit HEX counter with LED Display
No:	4
Date:	10-Mar-2001

Pin	Direction	Description
SRC_CLK	IN	This is a 24Mhz input clock.
DISPLAY0[6..0] DISPLAY1[6..0]	OUT	Two seven segment displays. Display zero is the high order display and display one is the low order display.
CLR	IN	When asserted "low" this pin should reset the count to "00."
RUN	IN	When this pin is asserted "high" the counter runs, when it is "low" the counter should hold its count.
DIR	IN	When this pin is asserted "high" the counter should count "up" (from 0 up), when it is "low" the counter should count down from "FF" to 0.