FPGA Design -- HEX Display

Project

8 Digit decimal counter with LED Display

No:
5

Date:
20-Mar-2001

Design a 32 bit ( 8 decimal digits!) counter that displays its count on an eight digit, multiplexed LED display. The counter should count at a rate of 10 counts/second and display a decimal point between digits 7 and 8. Use the CLOCK_10HZ and HEX_DISPLAY entities in this project. Include the ability to optionally blank leading zeros on the display. The pin-out for this chip is as follows:

Pin Direction Description

SRC_CLK
IN
This is a 24Mhz input clock.

SEGS[6..0]
OUT
These lines connect to the common 'segment' lines of the multiplexed LED display.

DIGITS[7..0]
OUT
These lines connect to the common 'enable' lines of the multiplexed LED display.

BLANK
IN
When asserted "high" this pin enables leading zero suppression on the display.

RST IN When this pin is asserted "low" the counter resets to 0.

TEST IN When this pin is asserted "high" all of the LEDs in the display light up.

DP OUT This signal connects to the common "decimal point" input of the multiplexed displays.

This project is most easily accomplished by breaking it up into a number of sub components that are each testable on their own. You will be re-using parts from the other projects so that will aid your implementation.

Purpose

This project is actually useful. Back in the day one could sell a chip with these capabilities to a company that was building a frequency counter. In that scenario a frequency would be gated on to the 'src_clk' pin for a fix amount of time (say 1/10th of a second) and the resulting count would be displayed as the frequency.

Discussion

If you will recall the hex counter from the previous project this one seems similar at first, however there is an annoying problem: How does one count by tens?

Thus this project actually becomes two projects, the decimal counter half and the multiplexed digit display half. Both bring some interesting challenges into the mix.

The SRC_CLK input is again 24Mhz so the CLOCK_10Hz component can be used to turn that into a 10 hz counting clock, however you will need to feed it directly into the multiplexing display component so that the display can be scanned at least 100hz.

Leading zero suppression had me stuck for a moment until I realized that each digit "knows" when it is zero. Use that knowledge to implement supressing leading zeros, remember that the least significant digit is never suppressed (even when it is zero.)

Going Further

This circuit was a chip sold by National Semiconductor and others and used in a variety of multi-meters, frequency counters, etc. There are lots of interesting things you can do with it. Some other ideas::

Convert this counter to a frequency counter by adding in a gate/reset pin..

Do minute and hour roll-overs (turning it into a timer rather than straight seconds counter)

Support negative counts with a floating "minus" sign.

Set it up for counting 100ths of a second and then make a reaction speed timer by turning on an LED and waiting for the resulting button press by the user..

Copyright © 2001, Chuck McManis, All Rights Reserved

Project		8 Digit decimal counter with LED Display
No:	5
Date:	20-Mar-2001

Pin	Direction	Description
SRC_CLK	IN	This is a 24Mhz input clock.
SEGS[6..0]	OUT	These lines connect to the common 'segment' lines of the multiplexed LED display.
DIGITS[7..0]	OUT	These lines connect to the common 'enable' lines of the multiplexed LED display.
BLANK	IN	When asserted "high" this pin enables leading zero suppression on the display.
RST	IN	When this pin is asserted "low" the counter resets to 0.
TEST	IN	When this pin is asserted "high" all of the LEDs in the display light up.
DP	OUT	This signal connects to the common "decimal point" input of the multiplexed displays.